Method for the production of individual monolithically integrated semiconductor circuits

ABSTRACT

A method for the production of individual integrated circuit arrangements from a wafer composite is disclosed, whereby the wafer is fixed with the component side (FS) on a support, the individual circuit arrangements ( 21 ) are separated on the support body by the etching of separating trenches ( 27 ) and individually lifted from the support body. The semiconductor substrate ( 20 ) is reduced in thickness during the fixing of the wafer to the support body, preferably to a substrate thickness of less than 100 μm. A reverse face metallization ( 31 ) is deposited on the back face (RS) of the thinned substrate, preferably after separation of the circuit arrangements on the support body.

CROSS REFERENCE TO RELATED APPLICATIONS

Applicant claims priority under 35 U.S.C. §119 of German Application No.102 38 444.4 filed on Aug. 22, 2002. Applicant also claims priorityunder 35 U.S.C. §365 of PCT/EP03/008276 filed on Jul. 26, 2003. Theinternational application under PCT article 21(2) was not published inEnglish.

The invention relates to a method for the production of individualmonolithically integrated semiconductor circuits.

In the production of integrated semiconductor circuits, also referred tosimply as ICs or chips, a greater number of circuits are typicallyproduced simultaneously on a thin semiconductor wafer, as the substrate,which circuits are subsequently separated in a later method step,particularly by means of sawing or cutting the wafer. The ICs typicallyhave a plurality of components on a front face of the substrate, and aback face metallization on the back face, whereby the back facemetallization lies at reference potential and can be electricallyconnected with individual conductive surfaces on the front face, by wayof passage holes (vias) through the substrate.

In the case of a method known from U.S. Pat. No. 6,448,151 B2, theseparation of individual chips from a wafer takes place mechanically, inthat trenches are sawed into the wafer from the back face, using a thinsaw blade, which trenches reach so far into the substrate that evenafter the substrate is reduced in thickness, these trenches are stillpresent. Final separation takes place after the wafer has been turnedover, from the front face, again by means of sawing.

In the case of a method described in U.S. 2002/00 55 238 A1, trenchesare sawed into a wafer from the circuit side, and in the case of a waferglued onto an intermediate carrier with the circuit side, the substrateis worn away, from the back, to the desired thickness, whereby thetrenches sawed previously are so deep that after the substrate isreduced in thickness, the individual chips are separated from oneanother in the substrate plane. The chips, which are still located inthe glued laminate, are attached to a second carrier with the back face,and the first intermediate carrier is removed. Afterwards, theinterstices between the chips separated in the substrate plane are madedeeper by means of an upper partial layer of the second carrier, and thechips in the laminate of substrate and upper layer of the second carrierare individually removed from the lower layer of the second carrier.

In U.S. 2001/00 05 043 A1, exemplary embodiments are indicated, amongother things, in which the wafer is attached to a carrier with thecomponent side. After the substrate has been reduced in thickness fromthe back, vias and separating trenches are etched, and the back face isprovided with a back face metallization, over its entire area. A metalstrip that surrounds the individual components on the component sideserves as an etch stop in the region of the separating trenches andinitially bridges these separating trenches, so that the individualchips are still connected by way of the metallization and the metalframes on the component side. In a first example, the chips in thelaminate are turned over and attached to a carrier tape with the backface, and mechanically separated, in this position, along the remainingconnections by way of the metal strips. In another method of procedure,the separation of the metallic chip connections remaining in the regionof the separating trenches takes place with the component side facingthe carrier, and the elements are subsequently taken over onto a carriertape.

U.S. Pat. No. 4,722,130: A describes a method in which trenches aremechanically worked into the substrate from the component side, and thesubstrate is subsequently glued onto a first intermediate carrier. Afterthe substrate has been reduced in thickness from the back face, thinmaterial gates remain standing at the locations of the milled separatingtrenches, so that the substrate continues to form a rigid composite. Onthe back face, a semi-rigid connecting layer and a PVC carrier are thenapplied, and the first intermediate carrier is removed. By means ofheating and expansion of the PVC carrier, the remaining thin substrategates are torn open and the individual chips are mechanically separatedin this manner.

In U.S. Pat. No. 6,215,194, the individual chips of a wafer, which areglued onto a carrier, are separated by means of milling separatingtrenches in the substrate plane, and are removed from the composite bymeans of a separate separating tool, and pressed onto and glued onto achip carrier.

In the case of a method known from WO 99/25 019 A1 for reducing thethickness of wafers, separating trenches are worked into a semiconductorsubstrate from the component side, and the substrate is glued onto acarrier with the component side. Afterwards, the substrate is worn awayfrom the back face, all the way to the trenches.

In WO 01/03 180 A1, as well, trenches are made in the semiconductorsubstrate from the component side, whereby this can take place bothmechanically and by means of dry etching, and after the wafer has beenglued onto a rigid carrier, the back face is worn down all the way tothe trenches, so that the chips are present on the carrier, separated inthe substrate plane.

The present invention is based on the task of indicating an advantageousmethod for the production of individual monolithically integratedsemiconductor circuits.

The invention is described in the independent patent claim. Thedependent claims contain advantageous embodiments and furtherdevelopments of the invention.

The invention makes secure and stable handling of the wafer possible incritical method steps, particularly in the case of low thickness of thesubstrate. According to an advantageous embodiment, the substrate isreduced in thickness to a substrate thickness of less than 100 μm, aftercompletion of the semiconductor circuits, including the conductivesurfaces and, if necessary, passivation of the front face. This isparticularly advantageous for semiconductor circuits on a GaAssubstrate, since GaAs possesses low heat conductivity, and the removalof waste heat to a heat sink, during operation, is significantlyimproved in the case of a low substrate thickness. Because of the lowsubstrate thickness, the opening cross-section of the passage holes thatwiden from the front face to the back face is also reduced, so that thepacking density of the circuits can be increased in the case of the thinsubstrate.

Attachment of the wafer to a rigid carrier before reducing the thicknessof the substrate guarantees stable and secure handling even in the caseof very low substrate thickness brought about by great reduction inthickness of the wafer. In particular, even non-level deformation of thewafer due to thermal influences or, in particular, also due to internalmechanical stresses in the semiconductor material, as they are typicalfor hetero-structure semiconductor layer sequences, is avoided.

It is advantageous that an electrical function test, particularly withregard to high-frequency behavior, is also performed only afterseparation of the individual components and thereby when the back facemetallization is present and interfacial connections through the passageholes, on completely connected units, has taken place.

Attachment of the uniform wafer to the rigid carrier, which can be asapphire, for example, takes place by means of an attachment layer madeof preferably adhesive material, particularly an adhesive, a paste, agel, or the like, which can also follow uneven parts of the surface ofthe wafer front face, which has been passivated, if necessary. Anadhesive attachment material whose adhesion to the front face of thewafer is lower at greater temperatures is preferred. Individual releaseof the mechanically separated ICs from the carrier preferably takesplace by means of mechanical lifting, overcoming the adhesion force, forwhich purpose the IC is heated, preferably by way of the carrier body,in the case of the preferred attachment material, in order to reduce therelease force. To release the individual ICs, it is advantageous to usea tool in the manner of vacuum tweezers.

It is advantageous if the several ICs of a wafer attached to a carrierare separated laterally in the wafer plane, in such a manner thatseparating trenches are etched from the back face of the substrate,which faces away from the carrier body, which trenches advantageouslyreach at least to or into the attachment material. During etching of theseparating trenches, it is advantageous if lateral under-etching isproduced in the attachment material, underneath the wafer. This makes itpossible to deposit the metal for the back face metallization and theinterfacial connection after completion of the separating trenches, aswell, over the entire area, without any metallization bridge beingformed over the separating trenches. The metallization layer isinterrupted at the steps that occur at the under-etchings.

According to a particularly advantageous embodiment, the passage holesthrough the substrate and the separating trenches can be produced in acommon etching process, particularly using a common photolithographicetching mask and/or at least partially common etching agents. In thisconnection, advantage can advantageously be taken of the fact that inthe case of conventional etching of the passage holes, the conductivesurfaces on the front face act as an etch stop, and no conductivesurfaces are provided in the regions between adjacent ICs of the wafer,so that etching continues into the attachment material in the region ofthe separating trenches, while it stops at the conductive surfaces ofthe front face in the region of the passage holes. This results in aparticularly simple course of the method.

After individually lifting the ICs separated in the substrate plane, asindividual chips, from the carrier body, the chips are individuallytreated further; this can include, for example, cleaning procedures, butparticularly also testing procedures with optical surface testing andelectrical function testing, for example. It is advantageous if the stepof optical testing simultaneously includes orientation of the chips in adefined position for tip contacting, for the electrical function test.The tested chips can be deposited onto intermediate carriers, which areknown as “blue tape” or “gel pack,” for delivery to the customer and/orintermediate storage, or can be installed into circuit modules directly,without such an intermediate step.

In the following, the invention will be explained in greater detailusing preferred exemplary embodiments. The drawings show:

FIG. 1 a side view of a wafer on a carrier,

FIG. 2 a preferred back treatment of a wafer,

FIG. 3 the treatment of separated integrated circuits.

FIG. 1 shows a side view of a cross-section through a dielectric carrierbody TR, for example a sapphire, and through a wafer WA, which containsa plurality of individual integrated circuits having semiconductorcomponents and metallic conductive surfaces on the front face FS of asemiconductor substrate HS.

The wafer WA is covered with an inorganic protective layer 23 on thefront face FS that faces down in FIG. 1. The surface of the carrier bodyTR that faces the wafer is provided with a glue material. The wafer ispressed onto the glue material with the surface of the protective layer23, and fixed in place adhesively by this material, on the carrier TR.After fixation of the wafer on the carrier, the substrate is reduced inthickness from the back face, which faces away from the carrier, to thethickness indicated with the broken line, particularly to less than 100μm (arrows DS), preferably by means of grinding.

In FIG. 2, the starting point is a wafer still fixed in place on thecarrier body by way of the glue material 24, with the substrate reducedto the desired thickness. The carrier body itself is no longer shown inFIG. 2, in order to make the illustration clearer.

In FIG. 2 a) to e), a detail having a separation region TB between twoadjacent integrated circuit regions IB_(N) and IB_(N+1) is shown, ineach instance, in a side cross-section view, in the left half of thefigure, and a detail from a region IB_(N) of an integrated circuithaving interfacial connections with passage holes is shown in the righthalf of the figure. The drawings are not to scale.

On the front face of the substrate 20 that has been reduced inthickness, facing the carrier body, the circuit plane having conductivesurfaces 22 is indicated as 21; it is covered by the protective layer 23(FIG. 2 a).

On the back face RS of the substrate 20 that has been reduced inthickness, a photoresist layer PL was applied, and first openings 25 forseparating trenches were structured in the separation region TB, andsecond openings 26 for passage holes to conductive surfaces werestructured in the circuit region IB of the individual integratedcircuits.

In a first common etching step, using the structured photoresist layerPL, separating trenches 27 are etched clear in the separation region TB,and passage holes 28 through the semiconductor substrate 20 are etchedclear in the circuit region IB. The etching parameters are adjusted insuch a manner that the passage holes narrow conically from the back faceRS towards the front face, with slanted flanks. This manner of etchingpassage holes is generally used. The etching process for the passageholes automatically stops at the conductive surfaces 22 of the circuitplane 21 in the circuit region IB, because of the selection of theetching agent and the adjustment of the etching parameters, whereas theetching process continues into the protective layer 23 in the separationregion TB, in which no such conductive surfaces are present (FIG. 2 c).

The etching process is continued in a second etching step, preferablywith a change in the etching agent and/or a change in the etchingparameters, whereby preferably, the substrate material is not removedany more and whereby the conductive surfaces 22 are not attacked in thecircuit region IB, whereas the material of the protective layer 23,under the separating trench 27, in the separation region TB, is removedin a depression that reaches to or into the glue material 24. Theetching agent and the etching parameters are selected in such a mannerthat the material of the protective layer is removed even laterallyunder the substrate 20, so that an overhang 30 a is formed by means ofunder-etching of the substrate. According to a preferred embodiment,etching of the depression 30 in the protective layer 23, including theoverhangs 30 a, takes place together with removal of the photoresistmask 29.

During the subsequent deposition of the back face metallization 31,which is directed over the entire area, the metal film 31 a that isdeposited on the glue material, in the depression 30, is interrupted bythe steps at the overhangs 30 a, as compared with the metallization onthe back face and side flanks of the substrate 20. In the passage holes,the back face metallization 31 forms a continuous metal film along theslanted edges, up to the conductive surfaces 22, in conventional manner,by way of which the conductive surfaces 22, contacted in this manner,can be laid to the electrical potential of the back face metallization31.

The integrated circuits laterally separated by the separating trenches27 that go through to the glue material (including the depressions 30)can be individually released from the glue material by means of arelease force that acts perpendicular to the substrate plane andovercomes the adhesion force of the glue material to the protectivelayer 23. By means of the selection of a glue material that demonstratesa clear reduction in adhesive strength when heated, and by means ofheating this glue material, preferably by way of the carrier body, theindividual circuit arrangements can be individually removed with lowrelease force, for further treatment. To lift the individual circuitarrangements off the carrier body TR, counter to a low adhesion force,and for their further handling, it is advantageous to use so-calledvacuum tweezers 4 as schematically shown in FIG. 3.

After a circuit arrangement (chip) IC has been lifted from the carrierbody TR (FIG. 3A), in the sequence of handling steps shown in FIG. 3,the chip IC, held on the back face with the vacuum tweezers 4, is turned(FIG. 3B) and cleaned by means of a solvent jet 5 (FIG. 3C), andsubsequently dried with inert gas (FIG. 3D). Another pair of vacuumtweezers 7 takes the chip over on the front face (FIG. 3E) and lays itonto the grounded electrostatic base plate 10 (FIG. 3F) with themetallized back face. The chip held electrostatically on the base plate10 is subjected to an automatic optical inspection 9 (FIG. 3G) and, inthis connection, advantageously adjusted in defined manner by means ofrotation and/or displacement of the base plate, or on the base plate inthe plate plane 8, and thereby oriented for a subsequent electricalmeasurement 11 (FIG. 3H).

The chips that pass the optical and electrical inspection can be setinto a storage or shipping area 13 (FIG. 3I).

The characteristics indicated above and in the claims, as well as thosethat can be derived from the figures, can advantageously be implementedboth individually and in various combinations. The invention is notrestricted to the exemplary embodiments described, but rather can bemodified in many different ways, within the scope of the ability of aperson skilled in the art.

1. A method for producing individual monolithically integrated semiconductor circuit arrangements from a water composite substrate comprising the following steps: (a) forming a plurality of separate component structures comprising monolithic semiconductor circuits and conductive surfaces on a front face surface of a wafer; (b) covering the front face surface of the wafer with a protective layer to form a wafer composite substrate; (c) attaching the water to a support via an attachment layer applied over the support; (d) reducing the substrate to a selected thickness; (e) producing passage holes through the substrate up to the conductive surfaces on the front face surface; (f) producing separating trenches between the monolithic semiconductor circuits up to or into the attachment layer, including removal of the protective layer under the separating trenches and lateral under-etching of the substrate; (g) depositing a back face metallization on a back face of the substrate and forming electrical connections through the passage holes; and (h) individually releasing the semiconductor circuits from the support for further individual processing.
 2. The method as recited in claim 1, wherein an adhesive material is used for the attachment layer.
 3. The method as recited in claim 2, wherein an adhesive material having a lower adhesion to the front face surface of the wafer at a higher temperature is used.
 4. The method as recited in claim 2 wherein the semiconductor circuits are individually released from the carrier mechanically by overcoming the adhesion force of the attachment layer to the front face surface of the wafer.
 5. The method as recited in claim 1, wherein the substrate is reduced in thickness to a thickness of less than 100 μm.
 6. The method as recited in claim 1 wherein the separating trenches are produced by means of a photolithographic etching process.
 7. The method as recited in claim 6, wherein a common photolithographic mask is used for the production of the passage holes and the separating trenches.
 8. The method as recited in claim 1, wherein the back face metallization is deposited after production of the separating trenches.
 9. The method as recited in claim 1, wherein an electrical function test of the semiconductor circuits is performed after separation. 